1. Field of the Invention
This invention relates to a method for making a leadframe package stand for converting area array CSP type packages into leadframe type packages.
2. Background Art
Leadframe type packaging for semiconductor ICs has been used for more than 30 years. The most popular leadframe packages are used with various integrated circuits including ASIC, CPU, memory, microcontroller and DSP. The corresponding packaging formats for such integrated circuits include QFP (quad flat pack), TSOP (thin small outline packages), QFN (quad flat no leadframe), and MLF (microleadframe) packages. Following the trends in semiconductor packaging and assembly, the IC size and signal output (I/O) pad pitches are shrinking with the package size and I/O lead pitch.
The function of metal, electrically conductive leads in the leadframe is to fan out the original IC bonding pads to a larger area that have wider pitches for the leads such that the leads are more suitable to interconnection to a printed wiring board (PWB). The most commonly used method of electrical interconnection between the individual leads of a leadframe and its IC bonding pads is wire bonding. For wire bonding, the terminal ends of each lead need to be located in proximity to the receiving bonding pad on the IC to receive a short wire loop therebetween. A jumping wire bridges the gap or separation between the IC pad and the lead terminal. In the case where flip chip bumping uses solder or some other conductive materials (e.g., gold stud bump, conductive polymer bump, and the like), the lead terminal must be located directly above or below the specific IC bonding pad to receive the bump for interconnection. Hence, the layout or pattern of the leadframe must account for fanning in the outer leads to the inner lead tips that are connected to the IC bonding pads.
To provide easy accessibility and manufacturability, the leadframe leads typically stay in parallel aligned directions but generally shrink in width. Typically, the inner lead tips are aligned with one another along a single row with the appropriate pitch to receive the connecting wires. For ICs having perimeter pads along all four side of the IC body, the inner leads are arranged along four single rows, one row for each side of the body, to receive the wires. Sometimes, to relieve the tight pitch, the leads can be “offset” or staggered to form two parallel rows such that the wires with a shorter loop are connected to the first or front row and the wires with a longer loop are connected to the second or back row. In other cases, even two or more layers of leads at different elevations are used in a three-dimensional array for wire interconnections in order to spread out the pitch.
For ICs that have centerline bonding pads such as those ICs that are made for dynamic random access memory (DRAM), the leadframe inner leads originate from two opposite sides and end in opposing rows that are in parallel alignment to the IC centerline bonding pads. As the rows of individual leads fan in, their widths shrink gradually in size to meet the narrower pitch of the IC pads. This kind of leadframe layout allows for low cost manufacturing by mechanical stamping from thin copper or alloy foils. Chemical etching may also be used to form the desired patterns.
As the IC sizes shrink and the IC I/O layout becomes more complicated, not all I/O pads will be located in the center or at the perimeter. There are flip chip bumped ICs that have I/O pad layouts in the format of an area array. There are also wafer level packages (WLP) that use a fan out layer to redistribute the I/O pads of the IC from the perimeter or centerline to an area array format. If the area array has a large pitch or a low number of I/Os, it is possible to shape the leadframe metal leads and form a corresponding area array pattern, for example, a 3×3 for a 9-I/O package or a 4×4 for a 16 I/O package. However, for many modern IC memory and ASIC applications, the I/O number is more than 50 and the IC body is reduced to a size of about 10×10 mm or smaller. For such conditions, it is very difficult and time consuming to achieve mass production of a stamped leadframe or even an etched leadframe with fine pitch (less than 200 um) and higher I/O (greater than 50) in an array-area format.
Therefore, it would be desirable to be able to make a leadframe type package by forming the individual inner leads in an area array format with very fine pitch and very small size to accommodate commercially available IC packages that are characterized by very small size and fine pitch in the area array, such as chip scale packages (CSP) and fine pitch ball grid array (FBGA) packages. It is also desirable to be able to use the leadframe package in known standard formats, such as TSOP, QFP or QFN, for accepting other CSP or WLP packages for vertical stacking of one package format on top of another to increase the electronic assembly density and performance without affecting the existing board level footprint or increasing the board area. Likewise, it would be desirable to be able to connect the flip chip IC directly to the individual inner leads while avoiding the space consuming wire bonds and the inherent disadvantages associated therewith, as in the case where a flip chip IC is used for stacking.